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Data Sheet April 20, 2004
LCK4310 Low-Voltage PLL Clock Driver
1 Features
s s s s s s s s
Output operating frequencies up to 1.25 GHz max. 100 ps part-to-part skew. 40 ps typical output-to-output skew. Cycle-to-cycle jitter 5 ps max. 3.3 V and 2.5 V compatible. Internal input pulldown resistors. Q output will default low with inputs open or at VEE. Meets or exceeds Joint Electron Device Engineering Council (JEDEC) specification EIA(R)/JESD78 IC latchup test. Moisture sensitivity level 1. Flammability rating: UL(R)-94 code V-0 at 1/8 in., oxygen index 28 to 34. Pin-for-pin compatible with ON Semiconductor(R) part number MC100LVE310.
To ensure that the tight skew specification is met, it is necessary that both sides of the differential output are terminated into 50 , even if only one side is being used. In most applications, all eight differential pairs will be used and therefore terminated. In the case where fewer than eight pairs are used and in order to maintain minimum skew, it is necessary to terminate at least the output pairs adjacent to the output pair being used. Failure to follow this guideline will result in small degradations of propagation delay (on the order of 10 ps--20 ps) of the outputs being used. While not catastrophic to most designs, this will result in an increase in skew. Note: The package corners isolate outputs from one another such that the guideline expressed above holds only for outputs on the same side of the package. The LCK4310, as with most ECL devices, can be operated from a positive voltage supply (VDD) in LVPECL mode. This allows the LCK4310 to be used for high-performance clock distribution in 3.3 V/2.5 V systems. Designers can take advantage of the LCK4310's performance to distribute lowskew clocks across the backplane or the board. In a PECL environment (series or Thevenin), line terminations are typically used since they require no additional power supplies. If parallel termination is desired, a terminating voltage of VDD - 2.0 V will need to be provided. An internally generated voltage supply (VBB pin) is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias ac coupled inputs. When used, decouple VBB and VDD via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.
s s
s
2 Description
The LCK4310 is a low-voltage, low-skew 2:8 differential emitter-coupled logic (ECL) fanout buffer designed with clock distribution in mind. The device features fully differential clock paths to minimize both device and system skew. The LCK4310 offers two selectable clock inputs to allow for redundant or test clocks to be incorporated into the system clock trees.
LCK4310 Low-Voltage PLL Clock Driver
Data Sheet April 20, 2004
3 Pin Information
3.1 Pin Diagram
VDDO Q0 Q1 Q1 Q2
20
25
Q0
24
23
22
VEE CLK_SEL
26 27
19
21
Q2
18 17 16 15 14 13 12
Q3 Q3 Q4 VDDO Q4 Q5 Q5
CLKa 28 VDD CLKa VBB CLKb
1 2 3 4
CLKb
NC
Figure 3-1. 28-Pin PLCC WARNING: All VDD, VDDO, and VEE pins must be externally connected to a power supply to guarantee proper operation.
2
VDDO
Q6 10
Q7
Q6 11
6
7
8
5
Q7
9
Agere Systems Inc.
Data Sheet April 20, 2004
3.2 Pin Descriptions
Table 3-1. Pin Descriptions Pin 1 2 3 4 5 6 7, 10, 12, 14, 17, 19, 21, 24 8, 15, 22 9, 11, 13, 16, 18, 20, 23, 25 26 27 Symbol VDD CLKa VBB CLKb CLKb NC Q[7:0] VDDO Q[7:0] VEE CLK_SEL Type Power PECL VREFOUT PECL PECL -- PECL Power PECL Power LVTTL I/O I O I I O O I
LCK4310 Low-Voltage PLL Clock Driver
Description ECL Differential Input Clock. Makes input pair with CLKa. Reference Voltage Output. ECL Differential Input Clock. Makes input pair with CLKb. ECL Differential Input Clock. Makes input pair with CLKb. ECL Differential Outputs. ECL Differential Outputs. ECL Input Clock Select. 0 = CLKa selected. 1 = CLKb selected. ECL Differential Input Clock. Makes input pair with CLKa.
-- Positive Power Supply.
-- No Connect. -- Positive Power Supply. -- Negative Power Supply.
28
CLKa
PECL
I
3.3 Logic Symbol
Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 Q5 Q5 Q6 Q6 Q7 Q7 VBB
CLKa CLKa CLKb CLKb CLK_SEL
CLK_SEL L H
Input Clock CLKa/CLKa Selected CLKb/CLKb Selected
Figure 3-2. Logic Symbol
Agere Systems Inc.
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LCK4310 Low-Voltage PLL Clock Driver
Data Sheet April 20, 2004
4 Absolute Maximum Ratings
Stresses which exceed the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods of time can adversely affect device reliability. Table 4-1. Absolute Maximum Ratings Parameter PECL Mode Positive Power Supply Input Voltage: PECL Mode Positive Input Voltage Output Current VBB Sink/Source Storage Temperature Range Wave Solder Symbol VDD VI IOUT IBB Tstg TSOL Conditions VEE = 0 V VEE = 0 V, VI VDD Continuous surge -- -- <2 s to 3 s at 248 C Min 0 0 50 -0.5 -65 -- Max 5 5 100 0.5 150 265 Unit V V mA mA C C
4.1 Handling Precautions
Although electrostatic discharge (ESD) protection circuitry has been designed into this device, proper precautions must be taken to avoid exposure to ESD and electrical overstress (EOS) during all handling, assembly, and test operations. Agere employs both a human-body model (HBM) and a charged-device model (CDM) qualification requirement in order to determine ESD-susceptibility limits and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used in each of the models, as defined by JEDEC's JESD22-A114 (HBM) and JESD22-C101 (CDM) standards. Table 4-2. ESD Tolerance Device HBM LCK4310 >2,000 V Minimum Threshold CDM >1,000 V
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Agere Systems Inc.
Data Sheet April 20, 2004
4.2 Thermal Parameters (Definitions and Values)
LCK4310 Low-Voltage PLL Clock Driver
System and circuit board level performance depends not only on device electrical characteristics, but also on device thermal characteristics. The thermal characteristics frequently determine the limits of circuit board or system performance, and they can be a major cost adder or cost avoidance factor. When the die temperature is kept below 125 C, temperature activated failure mechanisms are minimized. The thermal parameters that Agere provides for its packages help the chip and system designer choose the best package for their applications, including allowing the system designer to thermally design and integrate their systems. It should be noted that all the parameters listed below are affected, to varying degrees, by package design (including paddle size) and choice of materials, the amount of copper in the test board or system board, and system airflow. JA - Junction to Air Thermal Resistance JA is a number used to express the thermal performance of a part under JEDEC standard natural convection conditions. JA is calculated using the following formula: JA = (TJ - Tamb) / P; where P = power JMA - Junction to Moving Air Thermal Resistance JMA is effectively identical to JA but represents performance of a part mounted on a JEDEC four layer board inside a wind tunnel with forced air convection. JMA is reported at airflows of 200 LFPM and 500 LFPM (linear feet per minute), which roughly correspond to 1 m/s and 2.5 m/s (respectively). JMA is calculated using the following formula: JMA = (TJ - Tamb) / P JC - Junction to Case Thermal Resistance JC is the thermal resistance from junction to the top of the case. This number is determined by forcing nearly 100% of the heat generated in the die out the top of the package by lowering the top case temperature. This is done by placing the top of the package in contact with a copper slug kept at room temperature using a liquid refrigeration unit. JC is calculated using the following formula: JC = (TJ - TC) / P Table 4-3. Thermal Parameter Values Parameter JA JMA (500 lf/m) JC 63.5 43.5 27.3 Temperature C/Watt
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LCK4310 Low-Voltage PLL Clock Driver
Data Sheet April 20, 2004
5 Electrical Characteristics
5.1 dc Characteristics
Table 5-1. LVPECL 3.3 V dc Characteristics VDD = 3.3 V, VEE = 0 V. Input and output parameters vary 1:1 with VDD. VEE can vary 0.3 V. Devices are designed to meet the dc specifications shown in this table, after thermal equilibrium has been established. Parameter Symbol Min Power Supply Current Output High Voltage
*
-40 C Typ 55 2.295 1.605 -- -- -- -- Max 60 2.420 1.745 2.420 1.825 2.06 2.9 Min -- 2.275 1.490 2.135 1.490 1.92 1.8
25 C Typ 55 2.345 1.595 -- -- -- -- Max 60 2.420 1.680 2.420 1.825 2.06 2.9 Min -- 2.275 1.490 2.135 1.490 1.92 1.8
85 C Typ 65 2.345 1.595 -- -- -- -- Max 70 2.420 1.680 2.420 1.825 2.06 2.9
Unit
IEE VOH VOL VIH VIL VBB VIHCMR
-- 2.215 1.470 2.135 1.490 1.92 1.8
mA V V V V V V
Output Low Voltage* Input High Voltage (single-ended) Input Low Voltage (single-ended) Output Voltage Reference Input High Voltage Common-mode Range (differential) Input High Current Input Low Current
IIH IIL
-- 0.5
-- --
150 --
-- 0.5
-- --
150 --
-- 0.5
-- --
150 --
A A
* Outputs are terminated through a 50 resistor to VDD - 2 V. VIHCMR minimum varies 1:1 with VEE, maximum varies 1:1 with VDD. VIHCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level must be such that the peak-to-peak voltage is less than 1.0 V and greater than or equal to Vp-pmin.
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Agere Systems Inc.
Data Sheet April 20, 2004
Table 5-2. LVPECL 2.5 V dc Characteristics
LCK4310 Low-Voltage PLL Clock Driver
VDD = 2.5 V, VEE = 0 V. Input and output parameters vary 1:1 with VDD. VEE can vary 0.3 V. Devices are designed to meet the dc specifications shown in this table, after thermal equilibrium has been established. Parameter Symbol Min Power Supply Current Output High Voltage Output Low Input High Voltage (single-ended) Input Low Voltage (single-ended) Output Voltage Reference Input High Voltage Common-mode Range (differential) Input High Current Input Low Current
*
-40 C Typ 55 1.495 0.790 -- -- -- -- Max 60 1.620 0.955 2.400 1.030 1.361 2.1 Min -- 1.425 0.730 2.000 0.400 1.019 1.0
25 C Typ 55 1.507 0.820 -- -- -- -- Max 60 1.620 0.955 2.400 1.030 1.361 2.1 Min -- 1.425 0.730 2.000 0.400 1.019 1.0
85 C Typ 65 1.520 0.825 -- -- -- -- Max 70 1.620 0.955 2.400 1.030 1.361 2.1
Unit
IEE VOH VOL VIH VIL VBB VIHCMR
-- 1.425 0.730 2.000 0.400 1.019 1.0
mA V V V V V V
Voltage*
IIH IIL
-- 0.5
-- --
150 --
-- 0.5
-- --
150 --
-- 0.5
-- --
150 --
A A
* Outputs are terminated through a 50 resistor to VDD - 2 V. VIHCMR minimum varies 1:1 with VEE, maximum varies 1:1 with VDD. VIHCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level must be such that the peak-to-peak voltage is less than 1.0 V and greater than or equal to Vp-pmin.
Agere Systems Inc.
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LCK4310 Low-Voltage PLL Clock Driver
5.2 ac Characteristics
VDD = 3.3/2.5 V, VEE = 0 V, or VDD = 0 V, VEE = -3.3/2.5 V. VEE can vary 0.3 V. Table 5-3. ac Characteristics Parameter Symbol Min Maximum Toggle Frequency Propagation Delay to Output: In (differential)* In (single-ended)
Within Device Skew
Data Sheet April 20, 2004
-40 C Typ -- Max 1.25 Min --
25 C Typ -- Max 1.25 Min --
85 C Typ -- Max 1.25
Unit
fMAX
--
GHz ps
tPLH tPHL tSKEW tSKEW JITcyc-cyc JITp-p Vp-p tr/tf
525 500 -- -- -- -- 0.500 200
-- -- -- -- -- -- -- --
725 750 40 100 5 7 1 600
550 550 -- -- -- -- 0.500 200
-- -- -- -- -- -- -- --
750 800 40 100 5 7 1 600
575 600 -- -- -- -- 0.500 200
-- -- -- -- -- -- -- --
775 850 40 100 5 7 1 600 V ps ps ps ps
Part-to-part (differential) Jitter Input Swing
Skew
Output Rise/Fall Time (20%--80%)
* The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the differential output signals. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal. The within device skew is defined as the worst case difference between any two similar delay paths within a single device. Vp-pmin is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The Vp-pmin is ac limited for the LCK4310 as a differential input as low as 50 mV will still produce full ECL levels at the output.
Q DRIVER DEVICE Qb 50 50
D RECEIVER DEVICE Db
VEE
VEE = VDD - 2.0 V
Figure 5-1. Typical Termination for Output Driver and Device Evaluation
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Agere Systems Inc.
Data Sheet April 20, 2004
LCK4310 Low-Voltage PLL Clock Driver
6 Outline Diagrams
Dimensions are in millimeters.
12.446 0.127 11.506 0.076 PIN #1 IDENTIFIER ZONE
4 1 26
5
25
11.506 0.076 12.446 0.127
11
19
12
18
4.572 MAX SEATING PLANE 1.27 TYP 0.51 MIN TYP 0.330/0.533
5-2608 (F)
0.10
Agere Systems Inc.
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LCK4310 Low-Voltage PLL Clock Driver
Data Sheet April 20, 2004
7 Ordering Information
Table 7-1. Ordering Information Device LCK4310 Part Number LCK4310GF-DB LCK4310GF-DT Pin Count 28 28 Package PLCC PLCC Type Reel Tape Comcode 700020216 700020217
EIA is a registered trademark of Electronic Industries Association. UL is a registered trademark of Underwriters Laboratories, Inc. ON Semiconductor is a registered trademark of Semiconductor Components Industries, L.L.C.
For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com N. AMERICA: Agere Systems Inc., Lehigh Valley Central Campus, Room 10A-301C, 1110 American Parkway NE, Allentown, PA 18109-9138 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 CHINA: (86) 21-54614688 (Shanghai), (86) 755-25881122 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 6778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 1344 296 400
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Agere is a registered trademark of Agere Systems Inc. Agere Systems and the Agere logo are trademarks of Agere Systems Inc.
Copyright (c) 2004 Agere Systems Inc. All Rights Reserved
April 20, 2004 DS04-169LCK (Replaces DS03-158LCK)

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